Download Electronics Projects (No.21, 2006) - Magazine.pdf PDF

TitleElectronics Projects (No.21, 2006) - Magazine.pdf
Tags Bipolar Junction Transistor Transistor Data Compression Compact Disc
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Total Pages218
Document Text Contents
Page 109

ELECTRONICS PROJECTS Vol. 21 109

by 4). Please take care to place the IC in
the ZIF socket with proper orientation
and press ‘Next’. Depending on perform-
ance of all the gates of ‘IC under test’, the
message ‘GOOD’ or ‘BAD’ will appear on
its display.

For addressing peripheral devices
(8255, 8279), I/O mapped address scheme
has been employed. At EFY, the addresses
have been modified in accordance with the
Dynalog kit used for the purpose. Other
users would need to modify the program
address space as well as input-output
addresses for the peripherals suitably,
in accordance with the specific kit used

927F 79 MOV A,C
9280 FE02 CPI 02H ; CHECK IF ALL INPUT COMBINATIONS ARE
OVER
9282 C27792 JNZ LP2
9285 C3EB92 JMP GOOD ; OR JMP GOOD1
;NOr GATe CHeCK
9290 0E00 TYPE3: MVI C,00H ; SET GATE INPUTS
9292 79 LP3: MOV A,C
9293 07 RLC
9294 F601 ORI 01H ; SET GATE OUTPUT 1
9296 47 MOV B,A
9297 CDB192 CALL PROCESS
929A 0C INR C ; NEXT INPUT COMBINATION
929B 79 MOV A,C
929C FE04 CPI 04H ; CHECK IF ALL INPUT COMBINATION ARE OVER
929E C29292 JNZ LP3
92A1 C3EB92 JMP GOOD ; OR JMP GOOD1
92B1 3E89 PrOCess: MVI A,89H ; (8255 CONTROL WORD FOR CONFIGURING REG.
; A & B AS O/P AND REG. C (LOWER 4 BITS &
92B3 D30B* OUT 0BH ; UPPER 4 BITS) AS I/P)
92B5 D313* OUT 13H
92B7 78 MOV A,B
92B8 D308* OUT 08H ;OUTPUT THE COMBINATION FROM PORT A(A8255)
92BA D309* OUT 09H ;OUTPUT THE COMBINATION FROM PORT B(A8255)
92BC D310* OUT 10H ;OUTPUT THE COMBINATION FROM PORT A(B8255)
92BE D311* OUT 11H ;OUTPUT THE COMBINATION FROM PORT B(B8255)
92C0 16FF MVI D,FFH ; DELAY
92C2 15 LP4: DCR D
92C3 C2C292 JNZ LP4
92C6 DB0A* IN 0AH ; READ DATA INTO PORT C OF A8255
92C8 E63F ANI 3FH ; DON’T CARE FOR BIT 7 & 8
92CA BE CMP M ; COMPARE RESULT WITH DATA IN MEMORY
92CB C2DA92 JNZ BAD ; OR JMP BAD1
92CE 23 INX H
92CF DB12* IN 12H ; READ DATA INTO PORT C OF B8255
92D1 E63F ANI 3FH ; DON’T CARE FOR BIT 7 & 8
92D3 BE CMP M ; COMPARE RESULT WITH DATA IN MEMORY
92D4 C2DA92 JNZ BAD ; OR JMP BAD1
92D7 23 INX H
92D8 C9 RET
;resUlT DIsPlAY UsING 8279(bAD)
92DA 3E04* BAD: MVI A,04H
92DC D301* OUT 01H
92DE 3E7F* MVI A,7FH ; 7 SEG CODE-B
92E0 D300* OUT 00H
92E2 3E77* MVI A,77H ; 7 SEG CODE-A
92E4 D300* OUT 00H
92E6 3E3F* MVI A,3FH ; 7 SEG CODE-D
92E8 D300* OUT 00H
92EA 76 HLT
;resUlT DIsPlAY UsING 8279(GOOD)
92EB 3E04* GOOD: MVI A,04H
92ED D301* OUT 01H
92EF 3E3D* MVI A,3DH ; 7 SEG CODE-G
92F1 D300* OUT 00H
92F3 3E5C* MVI A,5CH ; 7 SEG CODE-O
92F5 D300* OUT 00H
92F7 3E5C* MVI A,5CH ; 7 SEG CODE-O
92F9 D300* OUT 00H
92FB 3E3F* MVI A,3FH ; 7 SEG CODE-D
92FD D300* OUT 00H
92FE 76 HLT
@ ;resUlT DIsPlAY UsING UTIlITY sUbrOUTINe OF KIT AT eFY(bAD)
9370 31FF9F BAD1: LXI SP,9FFFH
9373 210094 LXI H,9400H
9376 3E00 MVI A,00H
9378 0600 MVI B,00H
937A CD160B CALL OUTPT ; (UTILITY SUBROUTINE IN THE KIT TO
; DISPLAY ACC CONTENT)
937D 76 HLT
@ ;resUlT DIsPlAY UsING UTIlITY sUbrOUTINe OF KIT AT eFY(GOOD)
9380 31FF9F GOOD1: LXI SP,9FFFH

Fig. 3: PCB layout for interface

Fig. 4: Component layout for PCB

Page 110

ELECTRONICS PROJECTS Vol. 21110

by them. Such opcodes which are input-
output address dependent have been
annotated with an asterisk mark. The
alternate result-indicating subroutines
specifically used at EFY lab during testing
are also included for benefit of the readers.
The complete details of address space used
for the program and peripheral devices
are given before the actual program. The
program is self-explanatory, with suitable
comments added wherever required.

Although hardware interface circuit
can be assembled easily on a general-
purpose PCB, nevertheless an actual-size
single-sided PCB pattern for the same is
shown in Fig. 3 and its component layout
is given in Fig. 4. ❑

9383 211094 LXI H,9410H
9386 3E00 MVI A,00H
9388 0600 MVI B,00H
938A CD160B CALL OUTPT ; (UTILITY SUBROUTINE IN THE KIT TO
; DISPLAY ACC CONTENT)
938D 76 HLT
;DATA TAble
;NAND ;AND ;OR ;EXOR ;NOT ;NOR
9300 24 9310 00 9320 00 9330 00 9340 2A 9360 09
9301 09 9311 00 9321 00 9331 00 9341 15 9361 24
9302 2D 9312 09 9322 2D 9332 2D 9342 15 9362 12
9303 2D 9313 24 9323 2D 9333 2D 9343 2A 9363 12
9304 36 9314 12 9324 36 9334 36 9364 24
9305 1B 9315 12 9325 1B 9335 1B ;BUFFER 9365 09
9306 1B 9316 3F 9326 3F 9336 1B 9350 00 9366 36
9307 36 9317 3F 9327 3F 9337 36 9351 00 9367 1B
9352 3F
;ICIC ;BADD ;GOOD 9353 3F
93A0 0C 9400 0D 9410 0D
93A1 01 9401 0D 9411 00
93A2 0C 9402 0A 9412 00
93A3 01 9403 0B 9413 0C
sYMbOl TAble :
A 9212 TYPE1 925E LP1 9260 TYPE2 9275
LP2 9277 TYPE3 9290 LP3 9292 PROCESS 92B1
LP4 92C2 BAD 92E0 GOOD 92F5 BAD1 9370
GOOD1 9370
NOTe: 1. * INDICATes THAT OPCODe Is DePeNDeNT ON I/O ADDress UseD
IN THe sPeCIFIC KIT
2. @ INDICATes THe rOUTINe MODIFIeD bY eFY FOr DYNAlOG KIT

TAble II: lOGIC sTATes OF 8255 POrTs
8255 (A) 8255 (b)
ZIF socket Pin No. 6 5 4 3 2 1 13 12 11 10 9 8
reg. C Ports C5 C4 C3 C2 C1 C0 HEX C5 C4 C3 C2 C1 C0 HEX
reg. A/b Ports B2 B1 B0 A2 A1 A0 Eq. A0 A1 A2 B0 B1 B2 Eq.
O I2 I1 O I2 I1 I1 I2 O I1 I2 O
1 0 0 1 0 0 24 0 0 1 0 0 1 09
1 0 1 1 0 1 2D 1 0 1 1 0 1 2D
1 1 0 1 1 0 36 0 1 1 0 1 1 1B
0 1 1 0 1 1 1B 1 1 0 1 1 0 36

0 0 0 0 0 0 00 0 0 0 0 0 0 00
0 0 1 0 0 1 09 1 0 0 1 0 0 24
0 1 0 0 1 0 12 0 1 0 0 1 0 12
1 1 1 1 1 1 3F 1 1 1 1 1 1 3F

0 0 0 0 0 0 00 0 0 0 0 0 0 00
1 0 1 1 0 1 2D 1 0 1 1 0 1 2D
1 1 0 1 1 0 36 0 1 1 0 1 1 1B
1 1 1 1 1 1 3F 1 1 1 1 1 1 3F

0 0 0 0 0 0 00 0 0 0 0 0 0 00
1 0 1 1 0 1 2D 1 0 1 1 0 1 2D
1 1 0 1 1 0 36 0 1 1 0 1 1 1B
0 1 1 0 1 1 1B 1 1 0 1 1 0 36

O I O I O I I O I O I O
1 0 1 0 1 0 2A 0 1 0 1 0 1 15
0 1 0 1 0 1 15 1 0 1 0 1 0 2A

0 0 0 0 0 0 00 0 0 0 0 0 0 00
1 1 1 1 1 1 3F 1 1 1 1 1 1 3F

I2 I1 O I2 I1 O O I2 I1 O I2 I1
0 0 1 0 0 1 09 1 0 0 1 0 0 24
0 1 0 0 1 0 12 0 1 0 0 1 0 12
1 0 0 1 0 0 24 0 0 1 0 0 1 09
1 1 0 1 1 0 36 0 1 1 0 1 1 1B
I = INPUT; O = OUTPUT; Hex Eq = Hex digits read via Reg. C
Note:- Pin 7 of ZIF socket is connected to ground and pin 14 is connected to +5V.

IC Description

NAND (7400)
(Type 1)

AND (7408)
(Type 1)

Or (7432)
(Type 1)

ex-Or (7486)
(Type 1)

Invertor (7404)
(Type 2)

buffer (7407)
(Type 2)

NOr (7402)
(Type 3)

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